Purpose-built AI inference for modern data centers. Powering heterogeneous AI infrastructure with digital in-memory compute.
Santa Clara, CA
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d-Matrix Founder & CEO @sidsheth joined industry leaders at the @GlobalSemi (GSA) US Executive Forum for “The $700 Billion Bet — What Hyperscalers Want from the Semiconductor Industry.”
A timely discussion on what the next phase of AI infrastructure will demand from the semiconductor industry as AI scales.
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AI Infra Summit went beyond the show floor.
We welcomed a group of reporters and industry analysts to the d-Matrix office and lab for a closer look at what we’re building, from our silicon to our server racks.
Thank you to everyone who joined us for the lab tour.
#InfiniteInference #AIInfraSummit
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The path to infinite inference.
d-Matrix CEO @sidsheth took the Main Stage at #AIInfraSummit2026, while Satyam Srivastava and Chris Nicol joined discussions on low-latency inference and distributed AI infrastructure.
Thanks to everyone who joined us at Booth 722.
#AIInference #dMatrix
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Heterogeneous inference is here.
Stop by Booth 722 at #AIInfraSummit2026 to see how GPUs + d-Matrix are coming together to power AI inference at scale.
#AIInference #AIInfrastructure
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A great first day at #AIInfraSummit2026.
Today, d-Matrix Distinguished Engineer Satyam Srivastava gave a talk on how to close the inference efficiency gap, and Vice President Chris Nicol joined industry leaders for a discussion on operating distributed AI across compute, networking, and cloud-native platforms.
Join us tomorrow at Booth 722 and on the main stage to see d-Matrix CEO Sid Sheth give a keynote on “The Path to Infinite Inference” at 4:50pm.
#AIInference #AIInfrastructure #dMatrix
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Tomorrow at #AIInfraSummit2026, join d-Matrix at Booth 722 and on stage throughout the day.
“Solving the Inference Efficiency Gap” with Satyam Srivastava
🕚 Tuesday, September 15 at 11:00 AM
📍 Compute Track
“Operating Distributed AI” with Chris Nicol
🕝 Tuesday, September 15 at 2:20 PM
📍 Main Stage
“The Path to Infinite Inference” with Sid Sheth
🕔 Wednesday, September 16 at 4:50 PM
📍 Main Stage
#AIInference #AIInfrastructure #dMatrix
Made with AI
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Bloomberg Tech: d-Matrix joins NVIDIA’s AI inference push.
CEO Sid Sheth joins Ed Ludlow to discuss NVIDIA NVLink Fusion and why inference is becoming the next major battleground in AI compute.
Watch: bloomberg.com/news/videos/20…
#AIInference #NVLinkFusion #NVIDIA #dMatrix
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Big news: @dMatrix_AI is partnering with @nvidia.
Our next-gen Raptor XPUs with our path-breaking 3D DRAM stacked memory will plug directly into NVIDIA MGX rack-scale systems via NVIDIA NVLink Fusion — delivering ultra-low latency inference for premium token services.
Inference is an infinite opportunity, and it will demand a diversity of compute. Customers will be able to run a Raptor rack standalone, or alongside NVIDIA GPUs — matching the best compute to each phase of the workload.
Grateful to @JensenHuang and the NVIDIA team for building an open ecosystem that makes this possible. Let's go build the future!
🔗 d-matrix.ai/announcements/d-…
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Excited to work with NVIDIA to bring Raptor to NVIDIA MGX with NVLink Fusion. Building the next generation of AI infrastructure together.
🤝 @dMatrix_AI is adopting NVIDIA NVLink Fusion to connect its next-generation Raptor XPUs with NVIDIA AI infrastructure, joining a growing ecosystem of partners using our rack-scale architecture for AI factory-scale deployment.
By bringing together NVIDIA NVLink scale-up, Spectrum-X scale-out networking and the NVIDIA MGX rack architecture, d-Matrix can build specialized inference systems on a proven, rack-scale foundation spanning compute, racks, networking and software.
Learn more: nvda.ws/3SGWCyC
ALT d-Matrix Adopts NVIDIA NVLink Fusion for Rack-Scale XPU Deployment
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Big news for d-Matrix and AI inference.
We’re collaborating with NVIDIA to bring our next-gen Raptor inference XPUs into NVIDIA's MGX rack-scale infrastructure with NVIDIA NVLink scale-up interconnect. Ultra-low latency inference. Premium-level token services. Built to scale.
Read the full announcement: d-matrix.ai/announcements/d-…
#NVLinkFusion #AIInfrastructure #AgenticAI #dMatrix
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A great week in Taipei at SEMICON Taiwan 2026.
At the Memory Executive Summit, d-Matrix Vice President Chris Nicol joined leaders from across the semiconductor ecosystem to explore how memory is becoming an increasingly important part of AI system architecture.
Thank you to everyone who connected with us in Taipei for the thoughtful conversations.
#SEMICONTaiwan #AIInference #AIInfrastructure
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Congratulations to the @gimletlabs team on an incredible milestone. Their multi-silicon approach reflects where AI infrastructure is headed: purpose-built, heterogeneous, and designed around the demands of inference. Proud to be part of the journey.
A note from our co-founder and CEO @zainasgar on Gimlet Labs' $300M Series B.
This milestone belongs to the team building Gimlet Labs.
We’re hiring across the company as we scale our multi-silicon inference cloud. If you want to tackle some of AI infrastructure’s hardest problems and help build for the agentic era, join us: gimletlabs.ai/join_us
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d-Matrix will be participating in the CASPA 35th Annual Conference & CEO Summit this October.
Join CEO @sidsheth for the Edge AI & Intelligent Infrastructure panel alongside Krishna Rangasayee and Melton Chang, moderated by Dylan Patel.
📍 Santa Clara Convention Center
🗓 October 23
🕓 4:20–5:10 PM
#AIInfrastructure #EdgeAI
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d-Matrix is excited to join the AI infra Summit in Santa Clara, September 15–17.
@sidsheth, Chris Nicol, and Satyam Srivastava will take the stage across the summit to share perspectives on scaling low-latency inference, operating distributed AI infrastructure, and the path to infinite inference.
Join us for the sessions and stop by Booth 722 to meet our team and learn more about what we’re building for the next generation of AI inference.
#AIInfraSummit #AIInference #AIInfrastructure #dMatrix
Made with AI
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A great evening in San Francisco for AI Infrastructure, After Hours, following @anyscalecompute's Ray Summit.
Our VIP happy hour, co-hosted with @parasail_io, brought together founders, engineers, and AI infrastructure leaders for thoughtful conversations on inference, heterogeneous systems, and where the industry is headed next.
Thank you to the Parasail team and everyone who joined us.
#AIInference #AIInfrastructure #HeterogeneousComputing #dMatrix
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At #HotChips2026, d-Matrix shared a closer look at Raptor, our 3D DRAM architecture designed to bring memory and compute closer together, delivering 100+ TB/s of bandwidth with significantly greater energy efficiency.
@wccftech takes a deeper look at the architecture and what it could mean for scaling AI inference.
Read more: wccftech.com/d-matrix-raptor…
#AI #AIInfrastructure #Inference #Semiconductors
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We’re looking forward to bringing the AI infrastructure community together with the @parasail_io team at Ray Summit for AI Infrastructure, After Hours.
Join us this Wednesday in San Francisco at 5:30pm. RSVP below.
At Ray Summit this week? Join Parasail + @dMatrix_AI on Wednesday for AI Infrastructure, After Hours, a VIP happy hour for founders and engineers working across AI and inference.
Drinks, light bites, useful shop talk. 5:30–7:30 PM in SF.
RSVP: luma.com/tokenscarcity
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The trillion-dollar AI chip market is taking shape, and inference is opening up a new competitive landscape.
The AI infrastructure landscape is changing fast. @business for Bloomberg looks at @dMatrix_AI, @nvidia, @AMD, @Broadcom, @Google, @Amazon, @Meta, @OpenAI and others are shaping what comes next.
As our CEO @sidsheth shared:
“Inference is not a one-size-fits-all, so brute-forcing inference with a single chip is not going to work.”
The Age of Inference is here.
finance.yahoo.com/technology…
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A closer look at Raptor™ 3D DRAM from #HotChips2026.
@FiresideAlpha captured the discussion on how our 3D DRAM moves data 6–7x more efficiently than HBM4 on measured silicon, while delivering 100+ TB/s of bandwidth.
Watch the clip below for the technical breakdown.
#AIInference #3DDRAM #AIInfrastructure #dMatrix
Hot Chips 3D DRAM session: D-Matrix says its 3D DRAM moves data 6-to-7x more efficiently than HBM4 on measured silicon
"On comparing with HBM4, like we heard in the morning, we can get about 2.4 picojoules per bit energy efficiency on HBM4 of moving data into the base die."
"There's obviously additional energy burned to move the data sideways into the GPU, which is not counted here."
"But using this face-to-face stacking with 3D DRAM, we are able to reduce that energy to 0.37 picojoules per bit. This is a measured number."
"And so this gives us, you know, 6 to 7X energy efficiency."
"So for the same amount of power you can drive the bandwidth up, and so we were able to drive the bandwidth up here to 100 terabytes per second."
"And in this construction it's a single-high stack, and like I showed, even with 32 gigabytes of memory capacity we are able to solve SOTA models in a scale-up network."
"So no bits are wasted."
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At #HotChips2026, d-Matrix is presenting Raptor™, our 3D DRAM architecture built for the growing memory demands of AI inference.
Raptor brings memory closer to compute, delivering massive bandwidth with significantly lower I/O energy than HBM.
@ServeTheHome goes inside the architecture and the work behind Raptor: servethehome.com/d-matrix-ra…
#AIInference #AIInfrastructure #3DDRAM #dMatrix
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