Zeitlos #FPGA SOC/OS now has a Meshtastic client, seen here talking over LoRa with a Heltec V3 connected to a USB host port. zeitlos.org

I have Gemini CLI to build an ARM64 emulator from scratch and boot Linux to shell. Gemini has done it in 4.5 days (across 2 weeks). I’m amazed by Gemini’s ability in embedded programming world.

Wrote a M68020 CPU emulator for Tektronix TDS820 6GHz oscilloscope. Almost reach the shell prompt of VxWorks 4.0.2 OS. Ran out of time.

Pretty cool Japanese AI project funded by the government geniac.meti.go.jp/

With Codex, Claude, Gemini’s help, finally have come down this point…….. Fully recreated by AI from scratch, Tektronix TDS820, LeCroy WaveJet 324, and TDS1012 oscilloscope emulators. Original firmwares (I own these scopes) running on CPU emulators and with SDL wired up to their output.

HUGE release 1.0.0 for the #OpenXC7 open source FPGA toolchain! We are finally leaving @gatecatte 's 7 year old nextpnr-xilinx behind and are now fully based on upstream nextpnr with feature parity! github.com/openXC7/toolchain…

Today the Symbiotic EDA tool team achieved an awesome milestone within our uberWAVE-mixed-signal-viewer project. Can you spot it?

#SLogic32U3 Support up to 4CH 100M ADC module~ Compare wave display on oscilloscope and #ngscopeclient Get it in $99, follow project now: kickstarter.com/projects/sip…

Zeitlos #FPGA SOC/OS now has system-wide UTF-8 support, 22 keyboard layouts and a virtual keyboard. github.com/machdyne/zeitlos

FPGAマガジン特別版の味わい AIで開発特集はチャット形式からチーム形式での開発で検証ループを自動で回して…ってもうFPGAだからってのは関係ないな。大事なのは提示する仕様をきちんと明文化できるか。仕様が分からないものを作る場合はどうすればいいんだ

Connected 11 @AMD Kintex-7 FPGA cards running @apexcompute Unified Engine accelerator IP to test some big models on these cheap cards. 44 GB DDR3 with 22 Unified Engine cores totaling around 557 BF16 GFLOPs.

Apex Compute side project: DirectX driver up and running on our GPU prototype. It supports Vulkan 1.4 and DirectX 12.1. Fully developed in-house - 1 shader core (16-lane SIMD) - 2GB VRAM (fpga board limited) - GPU virtual addressing - DMA and raw PCIe DMA engines - Graphics front end - Triangle, line, and point rasterization - Conservative rasterization and VRS - Texture sampling, filtering, gather, and BC decode - Depth and stencil processing - 8-MRT ROP with blending and MSAA resolve - ROV and interlock support - Ray intersection assist - Independent display and scanout pipeline - HDMI output with HPD and DDC - Shader arithmetic and conversion units

Dělat FPGA s AI když všemu úplně nemusím rozumět je radost. Litex znám, FPGA a ZephyrRTOS taky. Tak jsem to navajboval na Cyclone 10 LP s 8MB SDRAM. Po startu se nakonfiguruje FPGA s Risc-V, z SPI FLASH se do SDRAM nakopíruje BIOS+Zephyr a prostě běží @enjoy_digital @ZephyrIoT

Spotted over on the @RadionaOrg #Gatemate FPGA Discord channel - the @intergalaktikEU ULX5M-GS boards! Ready for shipment.😎 Similar to the ULX4M (which instead has ECP5), both ride in any Raspberry Pi CM4 carrier. Nice boards 😍

White Rabbit project is awesome! But it was locked to uRV CPU and had to execute CPU firmware code from BRAM, which was not flexible and also not suitable for small FPGAs... This restriction has just been removed with recent LiteX-WR-NIC work: - Can now use one of the LiteX supported RISC-V CPU (ex VexRiscv). - Can now execute code from internal or external RAM (ex HyperRAM). github.com/enjoy-digital/lit…

Automating stereo camera calibration with an 🦾 SO-ARM101 ~ Do you want an $49 global shutter stereo camera with build-in NPU calculate depth map ready?

Debugging an hdmi output issue with my Fpga, so I gave Codex a webcam so it can see it without bothering me

Three generations of #SLogic in one photo — which one’s your pick? 👀 #LogicAnalyzer SLogic Combo8 40M@8CH SLogic16U3 800M@4CH ~ 200M@16CH SLogic32U3 1.4G@4CH ~ 200M@32CH kickstarter.com/projects/sip…

Everyone wants founders to be bold and brave, but not enough people expect the same from investors If your backers don’t have the balls to go alongside you no matter what, it’s just generational aura debt Respect to the VCs with aura, they don’t get enough credit

Made a breakout for an SSM2518 audio amp in a 0.5mm pitch QFN package that can push 2W per channel into a 4 ohm load on a 5V supply. Connected it up to the jetson, and configured the DTB for I2S output, and it works.. sounds surprisingly good too. They expose a register set for config and gain/attenuation over an I2C interface, which connects up to the Stemma QT port