香港天風國際證券分析師，分享科技產業趨勢觀察｜TF International Securities (HK) analyst sharing tech trend insights
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MediaTek’s latest announcement on the deepening of its long-term partnership with Nvidia repeatedly uses the term “rack-scale.” This is the key to understanding the announcement, and it directly validates the central conclusion of my research from more than two months ago:
MediaTek has upgraded the strategic positioning of its AI business from "IC / ASIC design" to "system-level design."
The announcement link:
mediatek.com/press-room/nvid…
The announcement also explains how MediaTek plans to put this new positioning into practice. By working with Nvidia, MediaTek can bring custom chips and XPUs into Nvidia’s mature rack-scale ecosystem, so that once chip development is complete, they can be integrated more quickly into rack-scale systems for deployment in data centers and AI factories.
For MediaTek, Nvidia’s mature rack-scale systems ecosystem means it does not need to start from scratch, giving this new strategy a much clearer path to execution.
For Nvidia, MediaTek’s custom silicon design capabilities and customer base can help extend Nvidia’s rack-scale ecosystem further into the custom silicon market.
This also explains why “rack-scale” is the key term in the announcement: it is where the two companies need each other most. MediaTek can move from chips to systems, while Nvidia can extend its rack-scale ecosystem into the custom silicon market, creating a win-win that opens up new growth opportunities for both.
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聯發科最新公告宣布深化與 Nvidia 的長期合作，其中反覆出現的「rack-scale」，正是理解這份公告的關鍵，也直接驗證了我兩個多月前研究的核心判斷：
聯發科內部已將 AI 事業的策略定位，從「IC / ASIC 設計」提升至「系統級別設計」。
公告網址：
mediatek.com/press-room/nvid…
這份公告也進一步說明，聯發科將如何執行這項新定位：透過與 Nvidia 合作，把客製化晶片 / XPU 導入 Nvidia 已成熟的機櫃級生態，讓客製化晶片在完成開發後，能更快整合成可部署於資料中心與 AI 工廠的機櫃級系統。
對聯發科而言，Nvidia 已成熟的機櫃級系統生態，使其不必從零開始，也讓新策略更具可執行性。
對 Nvidia 而言，聯發科的客製化晶片設計能力與客戶基礎，可協助其機櫃級生態進一步延伸至自研晶片市場。
這也說明了為何 rack-scale 是這份公告的關鍵字：這正是雙方最需要彼此的地方。聯發科藉此從晶片走向系統，Nvidia 則將機櫃級生態延伸至客製化晶片市場，形成雙方都能開拓新成長空間的雙贏局面。
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Just as the market had come to believe that Rubin CPX had been dropped from Nvidia’s product roadmap, my latest industry checks indicate that Nvidia has revived the program, with production expected to begin in 1Q27. Compared with the previous design, the revived Rubin CPX delivers stronger prefill performance and features major changes to both its GPU specifications and rack architecture, underscoring the high priority Nvidia places on prefill solutions.
Key changes:
1. Rubin CPX GPU specs
CPX delivers near-Rubin compute performance and matches Rubin’s maximum power rating of 2,300 W per GPU. CPX moves to 168 GB of HBM4, vs. 288 GB on Rubin and 128 GB of GDDR7 on the previous CPX design.
2. Rack design
The new CPX uses a standalone MGX ETL rack rather than sharing a rack with Rubin, as in the previous design. Customers can opt for 64, 128, 192, or 256 CPX GPUs depending on their needs. Within a CPX rack, each group of 64 CPX GPUs forms a rack module comprising eight compute trays (eight CPX GPUs per tray) and one switch tray.
3. Scale-up and scale-out
NVLink is used only for scale-up among the eight CPX GPUs within each tray, with 1–1.5 TB/s of NVLink bandwidth per CPX (vs. 3.6 TB/s per Rubin). Inter-tray scale-out within each rack module runs over Spectrum-6 Ethernet using all-copper L1 links. Across rack modules, scale-out is handled by each module’s Spectrum-6 switch over OSFP optical links.
4. How it works
CPX must be paired with Vera Rubin NVL72, and Nvidia recommends a 1:1 ratio of CPX to Rubin GPUs. CPX handles prefill and builds the KV cache, which is then transferred to Rubin over Ethernet RDMA for decode.
5. Product positioning: Best performance per dollar for long-context prefill
Over 50% of today’s AI inference workload comes from processing input context and building the corresponding KV cache. CPX therefore offers a more flexible, lower-cost way to handle prefill. Each eight-CPX tray has approximately 1.34 TB of HBM4, sufficient for most long-context prefill workloads and associated KV cache requirements.
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正當市場認為 Rubin CPX 已被 Nvidia 從產品藍圖中移除之際，我最新的產業調查顯示，Nvidia 已重啟 Rubin CPX，預計於 1Q27 開始生產。相較舊版，重啟後的 Rubin CPX 擁有更強的預填充（prefill）效能，GPU 規格與機櫃架構也都有明顯改變，足以證明 Nvidia 對 prefill 方案的高度重視。
關鍵改變如下：
1. Rubin CPX GPU 規格
CPX 算力接近 Rubin，單顆 GPU 最高功耗也同為 2,300 W。CPX 記憶體改為 168 GB HBM4，低於 Rubin 的 288 GB HBM4，但高於舊版 CPX 的 128 GB GDDR7。
2. 機櫃設計
新版 CPX 採用獨立的 MGX ETL 機櫃，不再像舊版與 Rubin 共櫃。客戶可依需求配置 64、128、192 或 256 顆 CPX。在 CPX 機櫃中，每 64 顆 CPX 組成一個機櫃模組，每個機櫃模組配置 8 個運算托盤（每個托盤有 8 顆 CPX）與 1 個交換機托盤。
3. Scale-up 與 scale-out
NVLink 僅用於同一托盤內 8 顆 CPX GPU 的 scale-up，每顆 CPX 的 NVLink 頻寬為 1–1.5 TB/s（vs. 每顆 Rubin 的 3.6 TB/s）。同一機櫃模組內的托盤間，透過 Spectrum-6 Ethernet（全銅 L1）進行 scale-out；跨機櫃模組時，則由各模組的 Spectrum-6 透過 OSFP 光纖進行 scale-out。
4. 運作方式
CPX 需與 Vera Rubin NVL72 搭配，Nvidia 建議 CPX 與 Rubin 的比例為 1:1。CPX 負責預填充（prefill）並建立 KV cache，再透過 Ethernet RDMA 傳給 Rubin 執行解碼生成（decode）。
5. 產品定位：長上下文 prefill 的最高性價比方案
目前 AI 推論工作量中，超過一半來自處理輸入內容（context）並建立相對應的 KV cache，因此，CPX 以更彈性的部署方式與更低成本承接 prefill。每個運算托盤（有 8 個 CPX）約有 1.34 TB HBM4，足以支援大多數長上下文 prefill 與 KV cache 建立需求。
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A recent media report claims that tight DRAM supply has left TSMC holding around US$1 billion worth of Apple 2nm processor work-in-process (WIP), described in the report as “processor wafers,” that cannot yet be packaged. As supporting evidence, it points to TSMC’s 2Q26 earnings call, where the company said the increase in inventory days was mainly due to the 2nm production ramp.
My industry checks suggest that Apple has indeed scaled back its hardware shipment plans this year due to memory shortages. However, Apple plans its processor production at TSMC at least three months in advance, based on the amount of memory expected to be available, rather than having TSMC build large amounts of WIP ahead of time.
This does not mean TSMC never builds WIP in advance and holds it in inventory. But if the bottleneck is not at TSMC, building ahead provides little benefit, so Apple would have little reason to pay TSMC extra for it.
In other words, tight memory supply is real. But my understanding is that there has been no dramatic scenario in which TSMC first built up US$1 billion of WIP and then had to wait for memory to arrive before packaging could proceed. TSMC and Apple are both known for world-class execution, and such a dramatic development would be unusual given how closely the two companies coordinate their supply chains.
Finally, public information alone offers a useful way to assess this claim. TSMC said on its 2Q26 earnings call that the increase in inventory days was mainly due to the 2nm production ramp. However, that inventory cannot be directly attributed to Apple processor WIP for three reasons:
1. TSMC's inventory days typically increase when a new advanced node enters its initial production ramp, so this is not unique to this year.
2. TSMC’s definition of inventory includes not only work-in-process, but also finished goods, raw materials, supplies, and spare parts.
3. Apple is not TSMC’s only 2nm customer this year. Other chip designers, including AMD and MediaTek, are also using 2nm.
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市場近期傳聞，台積電因 DRAM 供應緊張，囤積約 10 億美元的 Apple 2nm 處理器半成品（傳聞稱為處理器晶圓）無法封裝，並以台積電 2Q26 法說提到「庫存天數增加主因是 2nm 量產爬坡」作為佐證。
我的產業調查顯示，Apple 今年的硬體出貨量確實因記憶體短缺而下調，但 Apple 在台積電的處理器訂單，會在至少約 3 個月前依可取得的記憶體數量規劃生產，而不是讓台積電提前大量生產半成品。
這不代表台積電不會提前生產並囤積半成品；但若瓶頸不在台積電，這麼做並無實益，因此，Apple 也沒有太大理由額外付錢要求台積電這樣做。
換言之，記憶體供應緊張是真，但我的理解是，並沒有出現「台積電先囤積 10 億美元半成品，再苦等記憶體到貨封裝」這種戲劇性變化。台積電與 Apple 都是全球執行力頂尖的企業，在供應鏈管理上，雙方緊密合作下也很難出現這種戲劇性的發展。
最後，憑公開資訊也能反思市場傳聞可能性。台積電在 2Q26 法說表示，庫存天數增加主要因 2nm 量產爬坡，但這裡的庫存不能直接視為由 Apple 處理器半成品造成，原因有三：
1. 台積電過往全新先進製程量產爬坡時，庫存天數通常也會增加，並非今年特有現象。
2. 台積電的庫存除半成品外，也包括製成品、原材料、物料與備品。
3. 今年 2nm 客戶不只有 Apple，還包括其他 IC 設計客戶（如 AMD 與聯發科）。
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A few quick thoughts on what TSMC said about CoPoS during its Q2 2026 earnings call (screenshot from the transcript). The devil is in the details:
1. The phrase "alternative to try to lower down the cost" refers to the glass carrier. That's the CoP part.
2. "Work with substrate vendor" refers to the glass core substrate (GCS). That's the oS part.
3. Pay close attention to this phrase: "takes about another 1 year to be mature." It refers to the pilot line mentioned earlier. For a new technology, a mature pilot line and a mature mass-production line are two completely different things.
4. When TSMC says the pilot line will mature in about a year, this fully validates my earlier prediction that "the 510x515mm format will be used for pre-mass-production simulation in 2H27." For oS/GCS, "mature" means being able to start simulating with the final 510x515mm glass format on the pilot line, instead of the current 250x250mm.
5. Following from point 4, most companies currently involved in the oS/GCS supply chain may not be among the suppliers ultimately selected for mass production (not to mention companies that are only part of the market narrative and have no actual involvement). This is important to keep in mind when looking for investment opportunities at this stage, especially among equipment and materials suppliers.
6. TSMC's answer was brief, but it covered both CoP and oS. It did not mention a glass interposer at all, consistent with my earlier point that CoPoS does not use one.
7. Compared with what TSMC shared at its Japan symposium in June, the only new information in the Q2 2026 earnings call was that the pilot line is expected to reach maturity in 2H27. That said, I think the market was probably already expecting something close to this timeline. Now that TSMC has mentioned it, Ibiden and Innolux may also discuss the same timeline in their upcoming earnings calls.
Breaking down TSMC's glass core substrate slide
On June 11, at JPCA Show 2026 in Japan, TSMC gave a roughly 40-slide presentation titled "Advanced Packaging Technology Essential to the Evolution of AI" (AIの進化に不可欠な先端パッケージング技術). One slide from the deck, titled "Glass Substrate Development for CoWoS," has since leaked online and widespread attention.
Here's a closer read of that slide (see attached image). I'll skip the technical background that is already widely available. One thing to flag: the "COP" on the slide does not stand for Chip-on-Package. It means Coplanarity.
▌ Key conclusions:
1. TSMC has officially announced a partnership with Ibiden and Innolux to develop a glass core substrate. The structure is a three-layer design, a glass core sandwiched between two ABF build-up layers. This is the "oS" in CoPoS.
2. The market underestimates how important the glass core substrate is. It's a must-have capability for TSMC. In other words, within CoPoS the "oS" matters more than the "CoP", which is also why, when it was tested, it was paired with the existing CoW rather than with CoP.
3. The glass core substrate costs several times more per unit than existing ABF substrates. The glass processed by Innolux is very expensive per unit and is the single most critical material. Besides Nvidia, two US-based customers have also expressed strong interest.
▌ Industry checks tied to this slide:
1. The glass core substrate shown on the slide is cut from a full-size 250×250mm one. The ABF build-up layers mainly use Ajinomoto's GL107, mixed with ABF-GCP, and were tested at 24–28 layers, which is the mainstream ABF spec for AI chips in 2027–2028.
2. The CoW used in TSMC's experiment is a test vehicle. It is sufficient to validate the most challenging mechanical-structure issues that arise when working with composite materials. Good results mean TSMC, Ibiden, and Innolux have together broken through the critical technical bottleneck.
3. Ibiden currently handles cutting the 250×250mm glass core substrate. When the 510×515mm format is used for pre-mass-production simulation in 2H27, if Ibiden still wants to reduce production complexity to protect its ultra-high gross margins, it may hand the cutting over to Innolux, which is more familiar with the properties of glass.
▌ The leaked slide shows the validation results of pairing CoW with the "oS" in CoPoS, i.e., the glass core substrate (labeled "glass-SBT" on the slide). This addresses the "Substrate mechanical and electrical Dilemma" raised on the previous slide, and it strongly underscores how important the "oS" is within CoPoS.
1. Within CoPoS, what CoP solves is production efficiency / cutting economics, which ties to cost and price. What the oS solves is warpage and durability, which determines whether the chip can be made at all, and whether it can work.
2. CoP and oS complement each other well when integrated, but looking out over the next few years their technical roles still differ. CoP is a very-nice-to-have optimization, and going without it simply means a more expensive chip. But the oS is a must-have. Without it, even being able to make a usable chip is in doubt.
3. Comparing their roles isn't about elevating oS at the expense of CoP. It comes down to the practical question of which technical piece customers are willing to pay for. Details below.
▌ The real gold here is the power integrity (PI) improvement shown on the slide. This matters a great deal to customers, and it means that once glass core substrate production stabilizes, TSMC's profitability and competitive edge should rise in tandem.
1. How it works: the glass core substrate is thin → the vertical conduction path through TGV (through-glass vias) is short → conduction-path resistance (R) and loop inductance (L) both drop → PI improves.
2. Why it matters to customers: better PI → more stable power delivery → frees up power headroom → room to integrate more transistors, or to push clock speeds higher → more AI compute.
3. For customers, production efficiency is TSMC's basic responsibility, so they won't pay extra for it. But gains in AI compute translate directly into the customer's own competitiveness and profit, so customers are willing to pay for that. This is why Nvidia is so positive on the glass core substrate.
4. For TSMC, the glass core substrate raises yield and lowers cost while also boosting both the compute and the selling price of AI chips. It's both a cost-cutting tool and a pricing lever, a plus for profitability and competitiveness alike.
5. Substrate cost currently accounts for a low single-digit percentage of an AI chip's BOM, while losses from packaging yield run roughly 5–10× the substrate cost. So even if the glass core substrate ends up costing several times more than today's, its share of the BOM stays low, and it can cut the losses from packaging yield. The high unit price is therefore not expected to dampen customers' willingness to adopt it.
▌ In the Q&A after the presentation, an audience member asked about TGV details for the glass core substrate. TSMC declined to answer on the spot, because TGV is the key technology behind the glass core substrate, and the core know-how currently sits with TSMC and Innolux. By contrast, when another attendee asked about integrating IVR, eDTC, and LSI, TSMC answered at length.
▌ According to industry checks, if all goes well, TSMC is aiming to start mass production of the glass core substrate in 4Q28–1Q29, to match the cadence of Nvidia's AI chip iterations. As a side note: the Ibiden earnings presentation slide that many people have been circulating lists the glass core substrate timeline as CY30. My read is this: Ibiden, which has always been conservative and cautious in public, has now formally put the glass core substrate on its roadmap, which further confirms the long-term trend for this technology. That said, some other details on Ibiden's slide don't fully line up with what's known in the market. For example, its reticle timeline is off from TSMC's public claims by about a generation, and the Rubin Ultra substrate size is clearly larger than the 90×90 it marked for CY26–27. It's a reminder to always cross-check across multiple sources when forecasting the future.
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簡要評論台積電 Q2 2026 法說中關於 CoPoS 的部分（截圖自逐字稿），魔鬼都在細節中：
1. 「alternative to try to lower down the cost」指的就是 glass carrier（玻璃載具），也就是 CoP 的部分。
2. 「work with substrate vendor」指的就是 glass core substrate（GCS；玻璃核心載版），也就是 oS 的部分。
3. 「takes about another 1 year to be mature」這句話要非常注意，這是指延續上面提到的試產線。對新技術來說，試產線的成熟，跟量產線的成熟，是完全不同的兩回事。
4. 台積電提到試產線 1 年後成熟，完全驗證我先前提到「2H27 採用 510x515mm（玻璃尺寸）做量產前模擬」的預測。這裡的「成熟」，對 oS / GCS 來說，指的是能在試產線上，開始模擬使用 510x515mm 的最終玻璃規格，而非現在的 250x250mm。
5. 延續4，這意味著現在大部分參與 oS / GCS 的供應鏈，不一定是最終的供應商們（更別提只是純粹敘事、沒實質參與的供應商們）。這是現階段想找投資機會（特別是設備與材料商）時要注意的地方。
6. 台積電的回應很簡短，但已涵蓋了 CoP 與 oS。這之中完全沒有提到 glass interposer（玻璃中介層），也呼應了我先前提到 CoPoS 不使用 glass interposer 這件事。
7. 與台積電在 6 月份的日本研討會內容相比，Q2 2026 法說新增的資訊就是「2H27 試產線成熟」這件事。不過，我認為市場應該多少已經對這時程有預期。而既然台積電已經提了，接下來 Ibiden 與群創的法說，可能也會提及此時程。
重點解讀台積電的玻璃核心載板投影片
台積電在 6 月 11 日的日本 JPCA Show 2026，進行主題為「AIの進化に不可欠な先端パッケージング技術」的簡報，該份簡報約40頁，當中某張標題為「Glass Substrate Development for CoWoS」的投影片流出，引發廣泛關注。
以下是對該投影片（見附圖）的重點解讀，能網路科普查到的技術細節就不多說了，要注意的是投影片上的 COP 不是 Chip-on-Package 的縮寫，而是 Coplanarity、也就是平整度 / 共面度。
▌重點結論：
1. 台積電正式宣布與 Ibiden 以及群創合作，開發玻璃核心載板（glass core substrate），結構為玻璃上下各黏合 ABF 的三層結構設計，該技術就是用於 CoPoS 的 oS。
2. 市場低估玻璃核心載板的重要性，該技術對台積電是「must have」，意即 CoPoS 中，oS 的重要性高於 CoP，這也是該技術進行測試時，先搭配既有的 CoW 而非 CoP 的原因。
3. 玻璃核心載板單價較既有 ABF 載板高出數倍，群創加工的玻璃單價非常高，為最核心的材料。除 Nvidia 外，目前已有兩家美系客戶同樣表達高度興趣。
▌與本投影片相關的產業調查：
1. 本投影片提及的玻璃核心載板由 250x250mm 切割而來，ABF 增層主要採用 Ajinomoto 的 GL107 並混搭 ABF-GCP，以 2027–2028 主流 AI 晶片 ABF 規格的 24-28 層進行測試
2. 台積電實驗時的 CoW 是測試載具（test vehicle），足以驗證採用複合材料時最具挑戰性的機械結構問題。測試結果良好意味著台積電、Ibiden 與群創已合作突破關鍵技術瓶頸。
3. 目前是由 Ibiden 負責切割 250x250mm 的玻璃核心載板。待 2H27 採用 510x515mm 做量產前模擬時，若 Ibiden 仍想降低生產複雜性以維持超高毛利率，可能會改交由更熟悉玻璃特性的群創切割。
▌流出的投影片內容是將 CoPoS 中的 oS、也就是玻璃核心載板（投影片中的 glass-SBT）與 CoW 搭配的技術驗證結果，這是為解決該投影片前一頁所提到的「Substrate mechanical and electrical Dilemma」，而這顯著凸顯了 CoPoS 中 oS 的重要性。
1. CoPoS 中，CoP 要解決的是生產效率 / 切割經濟性的問題，這與成本與售價有關；而 oS 要解決的是翹曲與耐用性問題，這牽涉到能否做出晶片，以及晶片能否運作。
2. CoP 與 oS 兩者整合相得益彰，但展望未來數年，兩者的技術定位還是有些差異。CoP 是可選的絕佳優化選項（very-nice-to-have），沒有它的代價就是晶片更貴；但 oS 是必需品（must-have）， 沒有它可能連能否做出可用晶片都是問題。
3. 比較定位差異不是為了捧 oS 貶 CoP，這牽涉到客戶願意為哪個技術環節付錢的現實問題，細節下面分析。
▌投影片中含金量最高的是電源完整性（power integrity；PI）改善，這對客戶意義重大，這也代表玻璃核心載板生產穩定後，台積電獲利能力與競爭優勢可望同步提升。
1. 技術說明：玻璃核心載板薄 → TGV（through glass via）垂直導通路徑短 → 導通路徑電阻（R）跟迴路電感（L）同降 → PI 改善
2. 對客戶意義重大原因：PI 改善 → 供電更穩 → 釋出功率餘裕（power headroom）→ 可整合更多電晶體、或拉高運作時脈 → AI 晶片算力提升
3. 對客戶而言，生產效率是台積電的基本責任，客戶不會為此多付錢；但 AI 算力提升能直接轉化為客戶的競爭力與獲利，故客戶願意為此買單。這也是 Nvidia 積極看待玻璃核心載板的原因。
4. 對台積電而言，玻璃核心載板可提升良率並降低成本，同時提高 AI 晶片的算力與售價，既是降本工具，也是漲價籌碼，對獲利與競爭力都是加分。
5. 目前載板成本佔 AI 晶片 BOM 約低個位數，封裝良率造成的損失約載板成本的 5-10 倍，故即便未來玻璃核心載板成本高於目前的數倍以上，但佔 BOM 比重仍低，且可改善封裝良率造成的損失，故預期玻璃核心載板的高單價不會影響客戶採用意願。
▌簡報後的問答環節，有聽眾提問關於玻璃核心載板的 TGV 細節，台積電當場拒絕回答，因為玻璃核心載板的關鍵技術就是 TGV，核心 know-how 目前掌握在台積電與群創手中。相較下，另一個提問者的問題是關於 IVR、eDTC、與 LSI 的整合，台積電就回答了不少。
▌根據產業調查，若一切順利，台積電的目標是在 4Q28-1Q29 開始量產玻璃核心載板，以符合 Nvidia AI 晶片迭代節奏。順帶一提，許多人在傳的 Ibiden 的法說投影片，上面將玻璃核心載板時程列為 CY30，我對此的解讀是：對外向來保守謹慎的 Ibiden 將玻璃核心載板正式列為發展路線，這更確定了該技術長期趨勢。但從 Ibiden 投影片的其他細節與市場資訊不完全一致來看，例如 reticle 時程與台積電公開宣稱的差約一個世代、Rubin Ultra 載板尺寸明顯大於其在 CY26-27 標示的 90x90 等，這說明了在預測未來時，需隨時多方交叉驗證。
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In the fast-moving tech industry, can data from industry checks go six months without an update and still track a company’s guidance more closely than market consensus? That’s rare, but here’s one example where the research held up, with a little luck on my side.
ASML's latest Q2 2026 results further validate several predictions I made six months ago (in January). The most important of them, and the easiest to verify with hard numbers, is the EUV shipment outlook.
EUV is different from consumer electronics, where forecasts shift constantly. Strong AI demand and the difficulty of expanding upstream capacity mean that my EUV shipment estimates, based on capacity changes at the key supplier Carl Zeiss SMT, have stayed closer to the company's guidance than the market consensus over the past six months, even without any updates.
ASML's 2026 / 2027 EUV shipments:
1. In January, I forecast 2026 / 2027 shipments of 67 / 80-85 units, and noted that 2027 EUV was already sold out. At the time, the market consensus for 2026 shipments was just 53-55 units.
2. In its Q1 2026 results in April, ASML gave shipment guidance of at least 60 / 80 units for 2026 / 2027. Notably, the first time the company offered guidance as far out as 2027, the number already fell within my January forecast range.
3. In its latest Q2 2026 results in July, ASML raised the 2026 / 2027 numbers to about 65 units (excluding High-NA) / about 85 units (implied by the company's guidance), and noted that nearly all the EUV orders it needs for 2027 are already in, bringing the outlook even closer to my January forecast of 67 units for 2026 and "sold out" for 2027. Worth noting: even though more bullish expectations of around 90 units or more for 2027 had surfaced ahead of the Q2 2026 results, the outlook the company ultimately provided (about 85 units) still landed at the upper end of my January forecast range.
My latest supply-chain surveys indicate that Carl Zeiss SMT will significantly expand its EUV and higher-ASP immersion DUV optical system capacity by 20-25% YoY and 40-50% YoY, respectively, in 2027 to meet robust demand from ASML. Coupled with stronger-than-expected shipment outlooks for 2026, ASML's revenue is projected to reach €38–40bn in 2026 and €45–47bn in 2027, outperforming market consensus of ~€34–36bn and ~€41–43bn.
Key drivers behind the upside vs. consensus are as follows:
1. 2026 Growth Drivers:
➢ EUV and DUV shipments are estimated at 67 and 355 units, surpassing consensus of 53–55 and 310–320 units.
➢ Driven by strong 2nm demand, TSMC has upwardly revised its 2026 EUV orders twice: from an initial 22 units to 25 units last October, and currently to 28 units.
➢ To capture robust demand from Chinese memory makers, ASML plans to launch a new immersion DUV model NXT:1965i in 4Q26. As a down-spec version of the 1980i series, it complies with U.S. export controls while addressing Chinese clients' needs, serving as a key growth driver for 4Q26 and 2027.
2. 2027 Growth Drivers:
➢ 2027 capacity for both EUV and immersion DUV is currently fully booked thanks to the strong demand; further shipment upside will hinge on ASML’s supply-side improvements.
➢ Based on Zeiss SMT’s expansion, ASML’s 2027 shipments are projected to reach 80–85 EUV systems and 380–400 DUV systems.
➢ Boosted by the new 1965i launch, China’s procurement of high-ASP immersion DUV is expected to grow ~40% YoY in 2027.
3. Additional Upside Potential to Monitor:
➢ Potential ASP hikes for EUV and DUV systems amid prolonged supply tightness.
➢ Ongoing upward revisions for the new 1965i model from Chinese memory suppliers.
➢ Potential Intel Upside: The above estimates exclude incremental EUV demand from Intel. Although Intel has not officially placed orders (explaining its previously lower-than-expected Capex guidance), it has entered discussions with ASML for additional bookings. Intel's incremental EUV demand is projected at 20–30 systems over 2026–2027, of which 3–5 are High-NA EUV.
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在瞬息萬變的科技產業，有沒有什麼產業調查數據，即便經過半年不更新，仍能比市場共識更貼近公司展望？這很少見，但以下是一個經得起考驗、且多少帶點運氣成分的例子。
ASML 最新的 Q2 2026 財報，進一步驗證我半年前（1 月）的多項預測；其中最關鍵、也最能被量化檢驗的，是 EUV 出貨展望。
EUV 與變動頻繁的消費電子不同。AI 的強勁需求與上游擴產的難度，讓我藉由關鍵供應商 Carl Zeiss SMT 的產能變動所推估之 EUV 出貨量，即便沒更新，在過去半年仍能比市場共識更符合公司展望。
關於 ASML 在 2026 / 2027 年的 EUV 出貨量：
1. 我在 1 月預測 2026 / 2027 年出貨量為 67 / 80‒85 台，並指出 2027 年的 EUV 已銷售一空。當時市場對 2026 年出貨量共識為 53‒55 台。
2. ASML 在 4 月的 Q1 2026 財報中預估 2026 / 2027 年出貨量至少為 60 / 80 台。值得注意的是，公司首度公布更遠的 2027 年出貨展望，便已落在我 1 月預估的區間。
3. ASML 在最新的 7 月 Q2 2026 的財報中，將 2026 / 2027 年出貨量調升至約 65 台（不含 High-NA）/ 85 台（依公司展望推論），並指出 2027 年訂單已接近收滿，這與我 1 月時預測 2026 年的 67 台與 2027 年的「銷售一空」進一步吻合。值得一提的是，即便 Q2 2026 法說前一度傳出 2027 年出貨量約 90 台或以上的更樂觀預期，公司最終公告的展望（約 85 台），仍落在我 1 月預測的區間上緣。
我最新的供應鏈調查顯示，Carl Zeiss SMT (蔡司半導體) 為滿足ASML的強勁需求，將顯著擴增2027年EUV與較高ASP的浸潤式DUV光學系統產能分別約20-25% YoY與40-50% YoY，加上2026年EUV與DUV出貨優於預期，故預估ASML 2026與2027年營收將分別達到約380-400億與450-470億歐元，優於市場共識的340-360億與410-430億歐元。
以下是優於市場共識的關鍵原因：
1. 2026年關鍵動能：
➢ 預估EUV與DUV出貨分別達67台與355台，優於共識的53-55台與310-320台。
➢ 台積電因2nm強勁需求，接連兩次上修2026年EUV訂單，從最初的22台，於去年10月上修到25台，再到目前的28台。
➢ ASML為滿足中國記憶體廠商的強勁需求，預計在4Q26推出新款浸潤式DUV NXT:1965i。此新款DUV由1980i系列降規而來，同時符合美國出口規範並更能滿足中國記憶體業者需求，將貢獻4Q26與2027年動能。
2. 2027年關鍵動能：
➢ 受益於強勁需求，2027年的EUV與浸潤式DUV目前已銷售一空，能否再提升出貨量取決於ASML的供應改善狀況。
➢ 根據Zeiss SMT的擴產規劃，ASML在2027年的EUV與DUV出貨將分別達到80-85台與380-400台。
➢ 受益於新款DUV 1965i，中國對高單價浸潤式DUV採購量量在2027年成長約40% YoY。
3. 需關注潛在上調可能：
➢ ASML因供應緊張而調升EUV與DUV價格。
➢ 來自中國記憶體廠商強勁的需求，新款浸潤式DUV 1965i訂單仍在上修中。
➢ 以上分析未計入來自Intel的新EUV需求。Intel雖未就新需求正式下單 (故先前法說的資本支出低於預期)，但已跟ASML開始協調加單事宜。目前預估Intel對EUV額外需求在2026與2027年共20-30台 (其中3-5台是High-NA EUV)。
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I rarely make public calls on stock price trends (industry research and stock price forecasting are two entirely different things). One recent exception came ahead of WWDC26, when I said I was positive on Apple's share-price trend in 2H26 and added: "...regardless of what Apple says at WWDC26, as long as this core bull narrative stays intact, Apple's positive 2H26 share-price trend is unlikely to change."
After weathering a pullback triggered by the post-WWDC26 sell-the-news reaction and Apple's product price hikes, Apple shares still reached an intraday all-time high despite recent market volatility, consistent with the trend I forecast a month ago.
WWDC26 won't change Apple's positive 2H26 share-price trend, but it will test the staying power of the bull narrative
‒‒
1. Apple's core bull narrative right now is an almost intuitive market consensus that few people push back on: "Even if Apple is temporarily behind on AI, it will ultimately catch up and come out ahead."
2. Based on my latest supply-chain checks, I believe Apple's business momentum will remain strong through year-end, which should further reinforce the narrative into something like: "If Apple is doing this well without AI, just imagine once it has AI."
3. So regardless of what Apple says at WWDC26, as long as this core bull narrative stays intact, Apple's positive 2H26 share-price trend is unlikely to change.
4. That core bull narrative has its weak spots, but I think it has a good chance of holding at least through end-2026. How much longer it can last is what makes WWDC26 genuinely worth watching.
5. The key takeaway from WWDC26 will not be the short-term share-price reaction after the event. It will be whether Apple, using the same Gemini, can deliver better AI applications, agentic workflows, and on-device & cloud hybrid experiences than Google.
6. If the answer is yes, it would help extend Apple's core bull narrative. If the answer is no, it would suggest that Gemini sets the ceiling for Apple's AI experience. The stock may not necessarily turn bearish, but the "Apple will ultimately come out ahead" narrative would start to face growing scrutiny.
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我較少公開預測股價趨勢（產業研究與股價預測是完全不同的兩回事），一個近期少見的例子是我在 WWDC26 前指出正向看待 Apple 在 2H26 股價趨勢，且「...無論 Apple 在 WWDC26 上講什麼，只要這個多頭核心敘事沒有被破壞，Apple 2H26 的股價正向趨勢就不易改變。」
在經歷 WWDC 26 後的利多出盡、調漲 Apple 產品售價所導致的股價回檔後，加上面臨近期股市動盪，但 Apple 股價仍在盤中創了歷史新高，這與我在一個月前預測的趨勢一致。
WWDC26 不影響 Apple 2H26 股價正向趨勢，但將揭露多頭敘事的續航力
‒‒
1. Apple 目前的多頭核心敘事，是一個近乎直覺、沒什麼人反駁的市場共識：「即使 Apple 在 AI 進度上暫時落後，最終仍能後來居上」。
2. 根據最新的供應鏈調查，我認為 Apple 的業績將會好到今年底，而這會進一步強化多頭核心敘事成為：「Apple 沒有 AI 都這麼好，有了 AI 還得了！」
3. 因此，無論 Apple 在 WWDC26 上講什麼，只要這個多頭核心敘事沒有被破壞，Apple 2H26 的股價正向趨勢就不易改變。
4. 上述多頭核心敘事並非沒有破綻，但我認為至少有機會維持到 2026 年底。至於能維持多久，就是這次 WWDC26 真正值得觀察的地方。
5. 這次 WWDC26 的重點，不在於發表會結束後的短線股價反應，而是：同樣使用 Gemini，Apple 能否做出比 Google 更好的 AI 應用、agentic workflow、裝置端與雲端混合體驗。
6. 如果答案是肯定的，將有利於延長 Apple 的多頭核心敘事；如果答案是否定的，意味著「Gemini 決定了 Apple AI 體驗的上限」，則股價雖未必會轉空，但「Apple 終究會後來居上」的多頭核心敘事，將開始被更多人重新檢視。
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Goldman Sachs upgraded Nittobo to Buy in a July 6 report. One key reason was its cautious view on TSMC’s glass core substrate (GCS) progress. I won’t add much commentary here. Just sharing the note.
That said, my takeaway is that the other reasons GS cited for the upgrade do not really conflict with a constructive view on GCS over the next several years.
One thing to note: based on past patterns, the likelihood of TSMC providing major updates on GCS/CoPoS at its upcoming July earnings call may be low. This is especially true since TSMC just shared key R&D results at a Japan symposium in June, where it also made a rare mention of supplier partners. If that read is right, the likelihood of major GCS updates at Innolux’s and Ibiden’s August earnings calls may also be low.
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Goldman Sachs 在 7 月 6 日發布調升 Nittobo 評等到買進的報告，其中一個核心理由是保守看待台積電的玻璃核心載板（glass core substrate；GCS）發展。我先不多做評論，這邊單純分享訊息。
不過，我的結論是，從該報告其他的調升評等理由看，其實跟未來數年內正向看待 GCS 是不衝突的。
要注意的是，從過去歷史經驗看，台積電在接下來的 7 月法說，對 GCS / CoPoS 提供重大更新的機會可能不高，特別是才剛在 6 月份的日本研討會中，提供過關鍵研發成果且罕見提到合作供應商。如果我上述推論是對的，那更後面 8 月的群創與 Ibiden 法說，提供 GCS 重大更新訊息的機會也會連帶偏低。
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In this interview, Amazon hardware chief Panos Panay said the company is designing its own end-to-end silicon for some of its devices, while still sourcing chips from external suppliers such as Qualcomm.
This echoes the trend I previously predicted, that Amazon devices are moving toward in-house silicon. Another key takeaway is that Panay tied this effort to on-device AI, which suggests that beyond the cost considerations I noted earlier, in-house silicon is also a key part of Amazon's strategy for future AI devices.
cnbc.com/2026/07/02/amazon-a…
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在本訪談中，Amazon 硬體主管 Panos Panay 提到該公司正在為部分自家裝置設計自研晶片（end-to-end silicon），且目前仍向其他公司外購晶片（如 Qualcomm）。
這呼應了我先前預測的「Amazon 裝置走向自研晶片」趨勢。另一個重點是，Panay 也提到這是為了裝置端 AI，代表自研晶片除了我先前提及的成本考量外，也是未來 AI 裝置的重要布局。
cnbc.com/2026/07/02/amazon-a…
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This structural shift suggests that Amazon has been preparing for the long-term expansion of AI compute, and that it does not see AI compute oversupply as a real issue.
My latest industry checks indicate that Amazon’s processor procurement strategy for its own consumer electronics is set to undergo its first major shift in 20 years: moving away from externally sourced processors and adopting a COT (customer-owned tooling) model, with Alchip as the exclusive provider of back-end design and testing for its self-developed chips. Key points:
1. Amid the rapid expansion of AI compute, Amazon’s free cash flow for the 12 months ended 1Q26 fell 95% year over year to about US$1.2 billion. To maintain financial flexibility and keep funding its AI investment cycle, Amazon is also streamlining its organization and improving the cost structure of its non-AI businesses.
2. Amazon's own-brand consumer electronics, including Kindle, Fire TV, Echo, Alexa-enabled products, Blink, and Ring, currently use externally sourced processors. To optimize its cost structure, Amazon plans to gradually shift away from external sourcing and adopt a COT model similar to the one used for AI chip Trainium, taking more control of processor development in-house.
3. For this transition, Amazon has selected Alchip as its exclusive partner for back-end design and testing. Alchip is expected to receive non-recurring engineering, or NRE, fees for each design project, while also benefiting from processor shipments.
4. The strategy is expected to begin in 2027. Once the transition is complete, annual shipments of Amazon’s in-house processors are estimated at around 40 million units. This shift should help improve the cost structure of Amazon’s own devices and become a meaningful growth driver for Alchip.
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這個結構性的轉變，代表 Amazon 做好了為 AI 算力擴張的長期準備。意味著 Amazon 不認為有 AI 算力過剩的問題。
我最新的產業調查顯示，Amazon 自有消費電子的處理器採購策略，20 年來將首次有重大轉向：捨棄外購並改採 COT（customer-owned tooling）模式，世芯-KY 獨家提供自研晶片的後段設計與測試。幾個重點：
1. 受 AI 算力快速擴張影響，Amazon 截至 1Q26 的過去 12 個月自由現金流年減 95%，降至約 12 億美元。為維持財務彈性並支撐 AI 投資週期，公司正同步精簡組織並優化非 AI 業務的成本結構。
2. Amazon 自有消費電子產品，包括：Kindle、Fire TV、Echo、Alexa 裝置、Blink、Ring 等，目前採用的處理器均為外購。為優化成本結構，Amazon 決定將逐步停止外購，改採與 AI 晶片 Trainium 類似的 COT 模式，自行主導處理器開發。
3. 在此轉型過程中，Amazon 選定的合作對象為世芯-KY，由其獨家負責後段設計與測試。世芯-KY 除了會就各項設計專案向 Amazon 收取一次性工程費用（NRE），也會隨處理器的出貨受惠。
4. 此策略預計自 2027 年起啟動，待全面轉換完成後，自研處理器的年出貨量預估將達到約 4,000 萬顆，預期將有效改善 Amazon 自有產品的成本結構，並顯著貢獻世芯-KY 的營運動能。
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