I remember the project I learned verilog for. It took about six months of sleepless nights. Writing and rewriting the same thing, learning a lot (as usual) from my favorite kind of friends: the ones smarter than me -- low bar.
In the end, it did what I wanted, fit into my super small FPGA, ICE40HX4K, and felt like a monumental task.
Came back at it tonight. I was pleased that Astra found two bugs only, and both silly one-line fixes. But also realised that then it just didn't stop at whatever extreme requests I asked it to do. And all the stuff I was dreaming of implementing in the distant future are now commits in my hard drive.
Essentially, personal projects before 2025 feel like remains of a glorious, past civilisation.