CoWoS and package substrates get most of the attention, but the package still has to connect to a printed circuit board, Jett of @semivision_tw told us. Board-level problems can limit chip performance. Substrate makers, PCB suppliers and other partners have to coordinate their work, and the finished product must pass rigorous reliability tests. Integrating silicon photonics makes the job more complex. Jett sees advanced packaging and silicon photonics as two areas to watch over the next three to five years. He sees TSMC $TSM setting the direction at 2nm and beyond, while advanced packaging leaves room for a wider range of suppliers. Most work on 3D stacking is focused on memory, he says, because space inside the package is limited. Managing heat remains a challenge. Suppliers also have to develop next-generation technologies while keeping up with demand for their existing products.