News on semiconductors from around the world

🚨🚨🚨 INFIfab : India's first Microfabrication Translation Centre, advancing goals of India’s Semicon,Quantum, Supercomputing, and AI missions…….. Area : 96284 sq mtrs of clean room space Total funding : ~2000crs From 150 PhDs to 500 working on-site while 2x people trained
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entrackr.com/news/chiratae-v… Quanfluence raises $10M Series A fund to build a full-stack photonic quantum computer ( their technology does not require adv. minus zero refrigeration due to use of light hence operates the computer at room temp. )……….100qubit prototype by 2029.
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Nah they have silicon box & AMF !! Both solving bottlenecks pertaining to the ai era
"one in ten global chip output and one-fifth of global semiconductor manufacturing equipment production". Let us assume it's correct/close based on some criteria. Yet no Singapore HQed/owned big companies. An extreme "rent our space & infra" model digitimes.com/news/a20261006…
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Strong indication next Semicon investments would flow where
870-acre Silicon Valley coming up in Odisha. Another reason for investors in Hyderabad & Bengaluru to connect with Odisha and explore investment opportunities during the upcoming roadshows on 7th & 9th October. Odisha is building for the future. Are you ready to be part of it?
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Multi Nano sense technologies gets TDB funding for it’s MEMS gas sensor alongside a custom CMOS (AFeSoC)…….fusing 2 things together where MEMS interacts with gas molecules while the SoC tries finding type to tell which kind of toxic gas caused the leak. Extremely important tech
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A GaN fab under us-India defence initiative was planned with GF as the technology partner !! We need them to invest here now otherwise they’ll move to France or Singapore @AshwiniVaishnaw @SemiconIndia
Get them @GoI_MeitY to open a GaN fab in India . In the journey to be in at least the top-10 , we can't insist that all fabs should have Indian ownership digitimes.com/news/a20260929…
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Japs getting a proper memory fab after yrs now ……..should have been us moment 😔😔
[Exclusive] SK hynix Begins Groundwork on Japan Fab SK hynix has begun construction work for a memory semiconductor fab in Japan, just one month after the company said "nothing has been decided." According to industry sources on the 28th, SK hynix has reportedly started groundwork for a semiconductor fab in Japan's Tohoku region. "It's unclear whether it will be a standalone fab or a joint venture with Kioxia, but it's true that foundation work is underway on site," an industry source said. "It shows how strongly SK hynix wants to enter the Japanese market." The source added, "SK hynix has recently been asking domestic component suppliers to expand supply volumes. It's a sign the company is moving aggressively to respond to the memory supply shortage." As recently as a month ago, SK hynix said a memory fab in Japan was "under review" and that "nothing specific has been decided." If true, the company moved at remarkable speed, beginning site preparation within a single month. The Tohoku region is a major cluster for Japan's semiconductor and electronic components industries, with Iwate Prefecture at its core. Iwate hosts the Kitakami fab of Kioxia, a leading NAND flash maker, along with Japan Semiconductor, which makes microcontrollers (MCUs) and power MOSFETs, and Amkor Technology, which handles back end processing. Auto parts maker Denso and global chip equipment maker Tokyo Electron also have operations there. Adding the SK hynix memory fab now under construction would give the region a memory ecosystem spanning front end to back end processes. This is also why Tohoku emerged as a leading candidate after SK Group Chairman Chey Tae Won said in August that the group was considering a joint memory fab in Japan. At the time, Chey said SK was "considering anywhere with abundant power and water," which further raised the odds of a move into Tohoku. Iwate in particular is known for excellent water infrastructure, given the concentration of semiconductor companies there. If SK hynix builds a fab in Tohoku, Japan will complete a semiconductor triangle alongside TSMC in Kyushu and homegrown foundry Rapidus in Hokkaido, effectively linking the entire country through the semiconductor industry. Meanwhile, SK hynix maintains that nothing has been decided yet. "The Japan memory fab is currently under review," a company official said. "Nothing has progressed beyond that."
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Wrong !! Psmc’s P5 fab data is what Tata is after for 28nm and more adv. nodes !! Also, psmc regularly hits 85%+ yields for 45,55,65,90 & 110nm chips what Tata will start with !! So yes we overpaid but not by much
PSMC’s Fab IP masterclass. Took no risk, no investment and successfully got USD 620M from India. Now yield becomes Indian headache. Meanwhile, they have sold site to Micron where Indian engineers were to be trained and gained 1y DRAM tech from Micron. Enjoy the 90nm 😂
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NanoLogic retweeted
Intel 18A vs TSMC N2P: 18A Kicks Ass! We now have standard cell library metrics of N2P and 18A directly from Synopsys. Below is the chart that shows the logic densities and cell utilization of both N2P & 18A. Synopsys metrics attached below for reference. In HD, density difference between N2P & 18A is only around 6.8%. In HP, they're the same! In SRAM, they're the same! (38.1Mb/mm2) 18A-P is a performance enhanced version of 18A, does not improve density. Both 18A & 18A-P are design rule compatible. Similarly, N2P is a performance enhanced version of original N2, does not improve density. Both N2 & N2P are design rule compatible. When comparing logic densities of FSPDN & BSPDN process nodes, ignoring cell utilization is literally wrong, cos it gives completely wrong results. Simple reason is, FSPDN nodes (like TSMC N2P) have low cell utilization (lower than 75%) compared to BSPDN nodes (like Intel 18A) which have very high cell utilization (greater than 90%). If you're not using cell utilization when comparing densities, use effective densities instead. FSPDN nodes (like N2P) have a solid advantage when it comes to high frequency designs like Zen 6 & Nova Lake. The heat can easily dissipate directly thru the TIM/IHS. Whereas, BSPDN nodes (like 18A) have some hotspot issues cos the heat has to dissipate thru additional metal layer and then thru the TIM/IHS. This additional layer reduces Fmax by a bit. But by how much exactly is still unknown, cos we never had a high frequency desktop design on 18A coupled with a large heat sink. My guess is, 18A Fmax penalty is probably around ~10% compared to N2 variants. In essence, 18A is Intel's first true "2nm class" node. Share your thoughts. Follow/Repost if you like. 👍
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Great step ( it is not efficient but our only way to create a non-existent industry in India )…..hope they start replicating for all PSUs
⚡🇮🇳 𝐈𝐧𝐝𝐢𝐚 𝐢𝐬 𝐛𝐮𝐢𝐥𝐝𝐢𝐧𝐠 𝐭𝐡𝐞 𝐭𝐞𝐜𝐡𝐧𝐨𝐥𝐨𝐠𝐲 𝐭𝐡𝐚𝐭 𝐰𝐢𝐥𝐥 𝐩𝐨𝐰𝐞𝐫 𝐢𝐭𝐬 𝐏𝐨𝐰𝐞𝐫𝐠𝐫𝐢𝐝 ! 🇮🇳⚡ 𝐌𝐢𝐧𝐢𝐬𝐭𝐫𝐲 𝐨𝐟 𝐄𝐥𝐞𝐜𝐭𝐫𝐨𝐧𝐢𝐜𝐬 𝐚𝐧𝐝 𝐈𝐓 (𝐌𝐞𝐢𝐭𝐘), 𝐌𝐢𝐧𝐢𝐬𝐭𝐫𝐲 𝐨𝐟 𝐏𝐨𝐰𝐞𝐫 𝐚𝐧𝐝 𝐏𝐎𝐖𝐄𝐑𝐆𝐑𝐈𝐃 invites you for a Pre-RFP Stakeholder Consultation for the - indigenous design, development, qualification and supply of SiC MOSFET-based power modules for VSC-HVDC 🔌🔬 𝐊𝐞𝐲 𝐝𝐞𝐭𝐚𝐢𝐥𝐬: 👇 🔹 ~13,000 modules committed for pilot procurement, so there is an assured demand waiting 📈 🔹 3.3 kV, >1800 A base target, with a 4.5 kV higher-rating goal and a roadmap toward 6.5 kV 🚀 🔹 36-month development phase, leading to deployment in a pilot 1000 MW VSC-HVDC project 🏗️ 🔹 Field validation under real operating conditions ✅ 🤝 𝐖𝐡𝐨 𝐜𝐚𝐧 𝐚𝐩𝐩𝐥𝐲? Indian companies, including startups and MSMEs, individually or in consortia of up to 4 partners. Academia, national labs and R&D institutions can join as partners. 📅 𝐊𝐞𝐲 𝐝𝐚𝐭𝐞𝐬 ✍️ 𝐐𝐮𝐞𝐫𝐢𝐞𝐬 𝐚𝐧𝐝 𝐬𝐮𝐠𝐠𝐞𝐬𝐭𝐢𝐨𝐧𝐬 𝐝𝐮𝐞: 8 October 2026 (via email) 🏛️ 𝐒𝐭𝐚𝐤𝐞𝐡𝐨𝐥𝐝𝐞𝐫 𝐜𝐨𝐧𝐬𝐮𝐥𝐭𝐚𝐭𝐢𝐨𝐧 𝐬𝐞𝐬𝐬𝐢𝐨𝐧: 14 October 2026 (Delhi) This is a chance to shape the RfP itself and to help build strategic capability across the power semiconductor value chain, from device design to packaging to system integration. 💪 If you work in #SiC, #PowerSemi, #HVDC, #packaging, this is your moment. 🌟 👉 𝐅𝐮𝐥𝐥 𝐝𝐞𝐭𝐚𝐢𝐥𝐬: c2s.gov.in/HVDC.jsp #DigitalIndia #ChipsforViksitBharat #IndiaTechade @AshwiniVaishnaw @SecretaryMEITY
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This looks promising however will need some time to study the project……so far use cases stem for edgeAI & acc. To drive basic GUIs on low powered devices ( consider it as a secondary microcontroller ) If any one of u have the documents for this , pls share…it will help a lot
#IITDelhi Researchers Develop First Indigenously Designed Micro-Graphics Processing Unit (GPU) The #microGPU architecture developed by IIT Delhi researchers will enable indigenous graphics and display-processing systems for embedded applications. The project, led by M.Tech students Nammi Akash and M. Ravi Teja under the guidance of Prof. Jayadeva and Prof. Kaushik Saha from the Electrical Engineering Department, IIT Delhi, has demonstrated programmable graphics rendering using a custom floating-point GPU engine implemented entirely in Register Transfer Language (RTL) and mapped to a Spartan-7 Field Programmable Gate Array (FPGA) platform. “To the best of our knowledge, this is the first working, demonstrable indigenously designed micro-GPU from a university in India,” the researchers stated. The hardware architecture is a scalable programmable graphics processor IP suitable for applications such as industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats, educational e-book readers, and other affordable embedded visualization systems. It may be mapped to silicon ASIC or programmable hardware such as FPGAs. The team is exploring a roadmap towards an 8–16 core vector-style graphics processor architecture with an optimized compiler and graphics software toolchain, along with eventual migration to a proof of concept at a 65nm ASIC process node. The researchers believe that mature semiconductor process nodes such as 65 nm can potentially enable economically viable and practically useful indigenous graphics silicon for embedded systems applications. Read more at: shorturl.at/ixijx
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NanoLogic retweeted
GaN-based TRMM with 7 TRMs, each with peak power of 110W, developed by Alpha Technologies for GaN AEW&C upgrades. Alpha technologies was likely not selected for the contract either way because no contract with the company materialised
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NanoLogic retweeted
Korea’s #HBM-related exports to Malaysia jumped 5.7× YoY to US$1.62B in August alone. As pressure builds on Taiwan’s TSMC-centered packaging capacity, Malaysia is seizing the opportunity.💡More: pse.is/9mzscl 🔗
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IntelとTSMCは2027年第一四半期にいわゆる1.4nm(Intel14A ,TSMCでの呼称はA14)のリスク生産を始める。量産は2028年. 計画前倒しでサムスンやラピダス振り切る狙い.TrendForceが今までにメディア報道をわかりやすく図示⬇️
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NanoLogic retweeted
OnSemi increases its prices further. I expect industrial semi prices to continue increasing in 2027.
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A very very big misinterpretation 1. Fujifilm, Besi, JSR,etc are all suppliers to TATA for chemicals & eqp. 2. there is no vendor park apart from inox’s ASU right next door; 363 acres is the area in which Tata’s 3 fabs will be built hence trunk infra. Being created right now
Tata Electronics looks to capture the entire value chain in semiconductor manufacturing - across wafers, fabs, materials , chemicals and talent development.
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I hope govt pulls them apart to Atleast transfer LCD tech for a fab
India probes LG, Samsung over alleged tariff evasion on imported OLED TV parts economictimes.indiatimes.com…
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YMTCの源流企業・XMCはSpansionからの生産受託を通してNOR型フラッシュメモリの技術、続いてNAND型のそれを学んだ。当時、Spansionはサムスン電子とNAND型についてクロスライセンス契約を結んでいた。それが今ではYMTCがサムスン電子に“Xtacking Technology”のライセンス供与をしている世界なのだ。
NOR型フラッシュメモリメーカーのSpansionは破綻後に生産をXMCに委託していたが、Cypressを経てInfineon Technologiesの一部に。一方、XMCはYMTCに発展し、YMTCはフラッシュメモリの出荷量で2026年Q2に世界3位となった。元々、Spansionは富士通とAMDの合弁会社で、その工場は今は日本TI・会津工場だ。
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GAA is not everyone’s cut of tea……next are rapidus & intel !! We are heading for super consolidation like with GPUs - nvidia or niche materials - TOTO or ajinomoto
No wonder Samsung keeps going down in foundry market share. In spite of having an early start on GAA (at 3nm) compared to its rival, Samsung seems to have not earned the kind of trust TSMC has sammyfans.com/2026/09/23/qua…
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NanoLogic retweeted
Archgen Labs (@archgen_) is now backed by Y Combinator (@ycombinator) We are a research lab for silicon design, with one ambition: make chip design 1,000× faster. For decades, computing advanced by shrinking transistors. The next chapter for compute workloads will increasingly depend on building vertically - stacking active logic layers to create 3D chips. This makes designing those chips much harder but also opens up new possibilities for performance and efficiency. At @archgen_ , we’re bringing together foundational models, EDA tools, and physics-informed surrogate models to explore more designs, predict their behavior faster, and optimize how they’re built. Grateful to Kulveer Taggar (@kul), Garry Tan (@garrytan) and the @ycombinator team for backing us, and to the customers, mentors, and collaborators who have helped us get here. If you want to get to tapeout faster, we’d love to talk. DM us. #Semiconductors #OpenROAD #OpenLane #OpenSourceEDA #ChipDesign #VLSI #PhysicalDesign #AIForHardware #3DIC @naveen_venk
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