if you wanna work with me on making the next generations of claude better at hardware, we’re hiring!
zach
@blip_tm
Sep 22
i worked on this one! he's very smart and talks significantly more normal, go say hi

Sep 25, 2026 · 1:36 PM UTC

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job-boards.greenhouse.io/ant…

Research Engineer, Chip Design RL (Reinforcement Learning)

San Francisco, CA | New York City, NY

job-boards.greenhouse.io
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Replying to @blip_tm
Lol RIP EDA LLM cos
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Replying to @blip_tm
me on the first day that office demanding analog LLMs circuitry
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Replying to @blip_tm
So cool, I hope you all find someone great
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Replying to @blip_tm
@boardyai know anyone?
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Replying to @blip_tm
Can you do one for game design? I found that models really struggle to make good games so I’d love to help out with RL on that
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Replying to @blip_tm
are u doing layout codesign? using graph representation?
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Replying to @blip_tm
I really need to learn reinforcement learning
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Replying to @blip_tm
Can Opus 5.5 write a better systemverilog?
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Replying to @blip_tm
ah yes, pacing the frontier
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Replying to @blip_tm
How does thing work .. do have nay refs to learn about this tech .. i have built RL model for guidance of satellites its has simulator.. but chips does this works ?
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Replying to @blip_tm
claude: now available in solder
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Replying to @blip_tm
This is gonna be my dissertation for university's final project. Would love to apply some day.
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Replying to @blip_tm
Super interested! Can we do any related projects to make my resume look better
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Replying to @blip_tm
PICs considered or...?
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Replying to @blip_tm
Great area to work on!
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Replying to @blip_tm
Are you hiring interns for free? I want to switch to hardware side
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Replying to @blip_tm
all roads lead to anthropic huh
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Replying to @blip_tm
Is this for RTL design? Or are you guys tackling for chip design EDA tooling? Like place and route problems
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Replying to @blip_tm
does better at hardware mean passing timing closure, because plausible rtl is still prototype level
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Replying to @blip_tm @braindersnn
@bubbleboi
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Replying to @blip_tm
hey with the intention to collaborate in the pcb eda space
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Replying to @blip_tm
Do you ever fucking think about the hundreds of millions of children you're stealing their future from? Do you think about the billions, yes, billions, of people YOU are going to get killed? For shame. RESIGN.
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Replying to @blip_tm
I have a DB that has a few hundreds of findings of my own development. I also think neither Anthropic or openAI will develop a good chip design AI without serious partnerships, as most of the public RTL is trash. I think sonnet/luna level model could produce better RTL results than frontier with some changes.
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Replying to @blip_tm
Pacing the frontier.
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Replying to @blip_tm
I'm working on this in a few nearby universes. STA-aware RTL generation, EDA tool report/log processing, side agents for testability insertion, and secret sauce of custom circuit generation for critical paths when stdcells don't cut it.
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Replying to @blip_tm
Any public benchmarks the team is hill climbing on?
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Replying to @blip_tm
One day man…… One day!
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Replying to @blip_tm
Does inference on chip count? Systems for Capital superIntelligence.
Yeab - engg / core was in Palo Alto🌴
@yeabu369
Aug 28
checkout ipu.8tcap.com (inference processing units). working on building the foundational layer for inferencing. paper draft here github.com/yeabat8tcap/amazi…
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Replying to @blip_tm
@jaysidd it's coming
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Replying to @blip_tm
"yes this 2nm chip draw 3000W in simulated designs, that's on me, but here's the thing that nobody mentioned..."
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Replying to @blip_tm
How could I as a software engineer with an Electrical engineering background apply for research roles like these?
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